Power enhanced stacked chip scale package solution with integrated die attach film

ABSTRACT

An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to,PCT Application No. PCT/CN/2017/104496, filed on 29 Sep. 2017 and titled“POWER ENHANCED STACKED CHIP SCALE PACKAGE SOLUTION WITH INTEGRATED DIEATTACH FILM”, which is incorporated by reference in its entirety for allpurposes.

BACKGROUND

In current package architectures, power bond pads are located at theedge of the silicon die, increasing wire bonding density. Additionally,power pads compete for space with signal pads along the die edge. Powerdistribution requires traces routed from power pads located at the dieedge to points within the die, increasing trace density.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the disclosure will be understood more fully from thedetailed description given below and from the accompanying drawings ofvarious embodiments of the disclosure, which, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1A illustrates a cross-sectional view of a partially completeshingle die stack assembly with a double-layer die attach film (DLDAF)layer between two dies.

FIG. 1B illustrates a plan view of the shingle die stack of FIG. 1A,showing bond pads distributed on the upper die surface away from the dieedge, according to some embodiments of the disclosure.

FIG. 2A illustrates a cross-sectional view of an exemplary shingle diestack assembly having a spacer die on top, with DLDAF layers betweenadjacent dies, according to some embodiments of the disclosure.

FIG. 2B illustrates a cross-sectional view of an exemplary straight updie stack assembly with DLDAF layers between adjacent dies, according tosome embodiments of the disclosure.

FIG. 3A illustrates a cross-sectional view of a portion of DLDAF,according to some embodiments of the disclosure.

FIG. 3B illustrates a cross-sectional view of a portion of atriple-layer die attach film (TLDAF), according to some embodiments ofthe disclosure.

FIG. 3C illustrates a plan view of a die having power pads distributedover the top surface of the die, and covered by a section of DLDAF,according to some embodiments of the disclosure.

FIG. 4 illustrates a cross-sectional view of an exemplary shingle diestack with triple-layer die attach film (TLDAF) between adjacentdual-sided dies, according to some embodiments of the disclosure.

FIG. 5 illustrates a flow chart for a process flow for assembling a diestack with the DLDAF, according to some embodiments of the disclosure.

FIGS. 6A-6F illustrate cross-sectional views of an exemplary method ofassembling shingle die stack, according to some embodiments.

FIG. 7 illustrates a package with a Stacked Chip Scale Package (SCSP)comprising a DLDAF or a TLDAF in a vertical die stack, connectingmultiple dies as part of a system-on-chip (SoC) package in animplementation of a computing device, according to some embodiments ofthe disclosure.

DETAILED DESCRIPTION

A stacked chip scale package (SCSP) architecture is described employinga double-layer conductive die attach film (DAF) having at least oneconductive adhesive layer integrated with a non-conducting adhesivelayer for attaching dies in a vertical stack. In some embodiments, theinsulating layer is sandwiched between two conducting adhesive layers,forming a triple layer conductive DAF. In some SCSP implementationembodiments, the dies in the stack carry bonding pads on a top side.Accordingly, a double-layer conductive DAF is inserted between adjacentdies in a vertical die stack. The conductive layer adheres to the topside of the lower die and forms contacts with bond pads and terminalspresent on the top side. The insulating layer adheres to the bottom sideof the upper die, where no bond pads or terminals are present. In someembodiments, power bond pads and/or terminals are located along the topside of the dies at positions between the bonding edge and the rearedge.

In conventional die architectures, power bond pads are all located atthe bonding edge along with signal bond pads. Distributed power terminallayout may provide enhanced power delivery to the integrated circuitscarried by the die. The edge-located power bond pads are typicallyconnected to integrated circuits carried on or within the die byinternal trace metallization. The architecture of various embodimentsprovides for greater flexibility of design of integrated circuitscarried on or within the die. According to some embodiments, powerdelivery to the integrated circuits is furnished by external coupling,eliminating reliance on internal trace routing extending from the dieedge.

The conductive layer of the double-layer and triple-layer DAF provides asheet conductor that electrically couples one or more of the distributedpower bond pads and/or terminals together. In some embodiments, one ormore relay bond pads are located on the top surface near the bondingedge of the die, and in some embodiments, are connected to a wirebonding pad by a short internal trace. According to embodiments, therelay bond pad is externally coupled to the distributed power terminalsthrough the conductive layer of the double-layer DAF. In someembodiments, the relay pad is coupled to a single wire bonding pad onthe die edge by a short internal trace. Accordingly, power is deliveredto the power terminal pads from the relay pad through the conductivelayer. The conductive layer of the double-layer DAF electrically couplesthe multiple power terminals on the die to a single wire bond pad by theintermediary of the relay pad. Accordingly, wire bonding density at theedge of the die can be significantly decreased, as well as the number ofrequired bond pads located at the bonding edge of the die. According tosome embodiments, the conductive layer of the dual-sided DAF is a sheetconductor that is coupled to one or more power terminals on the diesurface that is covered by the DAF. In some embodiments, the conductivelayer of the DAF has a lower sheet resistance than power tracemetallization, thereby providing a low resistance current path from therelay pad to the one or more power terminals through the conductivelayer. The low sheet resistance of the conductive layer of thedual-sided DAF allows for lower I²R power losses that can result in lesslocal heating as well as smaller IR drop.

In some embodiments, the DAF is a triple layer film having an innerinsulating layer sandwiched between a first and second outer conductivelayers. The insulating layer isolates the first and second outerconductive layers, which form separate conductive adhesive sheets. Insome embodiments, a die stack assembly comprises dual-sided dies havingintegrated circuits on both sides of the die. In this implementation,the triple layer DAF is inserted between upper and lower adjacent diesin the vertical stack, the first conductive layer adhering to the topside of the lower die, and bottom side of the upper die.

In the following description, numerous details are discussed to providea more thorough explanation of embodiments of the present disclosure. Itwill be apparent, however, to one skilled in the art, that embodimentsof the present disclosure may be practiced without these specificdetails. In other instances, well-known structures and devices are shownin block diagram form, rather than in detail, in order to avoidobscuring embodiments of the present disclosure.

Note that in the corresponding drawings of the embodiments, signals arerepresented with lines. Some lines may be thicker, to indicate moreconstituent signal paths, and/or have arrows at one or more ends, toindicate primary information flow direction. Such indications are notintended to be limiting. Rather, the lines are used in connection withone or more exemplary embodiments to facilitate easier understanding ofa circuit or a logical unit. Any represented signal, as dictated bydesign needs or preferences, may actually comprise one or more signalsthat may travel in either direction and may be implemented with anysuitable type of signal scheme.

“Bond pad” is a term referring to electrical bond pads in associationwith test points or external electrical connections of an integratedcircuit. Related industry terms are “bond pad” and “bump”. “Solder bump”or “bump” is a ball of solder bonded to a bond pad for further assemblyof the die into packages by use of surface mount technology, or for wirebonding.

An associated term is “terminal”, having the meaning that it is areceiving contact for power or other electrical signals. For thepurposes of this disclosure, “terminal” indicates a signal or powersink, and is coupled to a signal or power entry point of an integratedcircuit. A terminal may be a bond pad for wire bonding or solder bumpattachment.

Throughout the specification, and in the claims, the term “connected”means a direct connection, such as electrical, mechanical, or magneticconnection between the things that are connected, without anyintermediary devices. The term “coupled” means a direct or indirectconnection, such as a direct electrical, mechanical, or magneticconnection between the things that are connected or an indirectconnection, through one or more passive or active intermediary devices.The term “circuit” or “module” may refer to one or more passive and/oractive components that are arranged to cooperate with one another toprovide a desired function. The term “signal” may refer to at least onecurrent signal, voltage signal, magnetic signal, or data/clock signal.The meaning of “a,” “an,” and “the” include plural references. Themeaning of “in” includes “in” and “on.”

The vertical orientation is in the z-direction and it is understood thatrecitations of“top”, “bottom”, “above” and “below” refer to relativepositions in the z-dimension with the usual meaning. However, it isunderstood that embodiments are not necessarily limited to theorientations or configurations illustrated in the figures.

The terms “substantially,” “close,” “approximately,” “near,” and“about,” generally refer to being within +/−10% of a target value(unless specifically specified). Unless otherwise specified the use ofthe ordinal adjectives “first,” “second,” and “third,” etc., to describea common object, merely indicate that different instances of likeobjects are being referred to, and are not intended to imply that theobjects so described must be in a given sequence, either temporally,spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases “A and/or B” and “Aor B” mean (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B and C).

Views labeled “cross-sectional”, “profile” and “plan” correspond to aorthogonal planes within a cartesian coordinate system. Thus,cross-sectional and profile views are taken in the x-z plane, and planviews are taken in the x-y plane. Typically, profile views in the x-zplane are cross-sectional views. Drawings are labeled with axes toindicate the orientation of the figure.

FIG. 1A illustrates a cross-sectional view in the x-z plane of a shingledie stack assembly 100 with a double layer die attach film between twodies. The section is taken along cut line A-A′ in FIG. 1B.

Dies 101 a and 101 b are vertically stacked in a shingle configurationwith edges offset in the x-dimension. In some embodiments, dies 101 aand 101 b comprise a semiconductor body from which integrated devicesare fabricated. In some embodiments, dies 101 a and 101 b comprisesilicon or other group IV elements, such as germanium. In otherembodiments, dies 101 a and 101 b comprise III-V compounds such as InAs,GaAs, InP GaP, GaN, etc. For clarity, two dies 101 are shown in diestack 100. However, die stack 100 may have any number of dies in thestack. Dies 101 a and 101 b are bonded to one another with double layerconductive die attach film (DLDAF) 102 disposed between dies 101 a and101 b. In some embodiments, DLDAF 102 comprises non-conductive adhesivelayer 103 over conductive adhesive layer 104. Dies 101 a and 101 binclude one or more power terminal pads 105 and relay pad 106distributed over top surface 107. According to some embodiments, relaypad 106 is connected internally to wire bond pad 108 by trace 109.

Conductive adhesive layer 104 of DLDAF 102 is disposed over top surface107 of dies 101 a and 101 b, (only die 101 a is shown as covered),covering power terminal pads 105 and relay pad 106 (shown for die 101 b,however, same description holds for die 101 a). According to someembodiments, conductive adhesive layer 104 is adhered to top surface107, and conformally adhering to power terminal pads 105 and relay pad106. In some embodiments, conductive adhesive layer 104 is a sheetconductor, and electrically couples power terminal pads 105 to relay pad106. Relay pad 106 is electrically connected to wire bond pad 108, towhich power may be delivered by a wire leading from the substrate (notshown) and bonded to wire bond pad 108. In some embodiments, power isdistributed to power terminal pads 105 through conductive adhesive layer104.

In some embodiments, bottom surface 107 of dies 101 a and 101 b has nometallization for external electrical coupling in the form of contactpads, and is not active electrically. For die attachment, non-conductiveadhesive layer 103 of DLDAF 102 is disposed under bottom surface 110 ofdies 101 a and 101 b. In some embodiments, non-conductive adhesive layer103 is a carrier or backing layer for conductive adhesive layer 104, andadheres to inactive bottom surface 110 of dies 101 a and 101 b tocomplete attachment of adjacent dies 101 a and 101 b. While not active,bottom surface 110 may exhibit conductivity, and must be isolated fromthe metallization on lower adjacent die by an insulating film.Non-conducting adhesive layer 103 serves this function.

FIG. 1B, illustrates a plan view of the shingle die stack 100 of FIG.1A, showing bond pads distributed on the upper die surface away from thedie edge, according to some embodiments of the disclosure.

In FIG. 1B, multiple power terminal pads 105 are distributed over topsurface 107 of die 101 b. In some embodiments, power terminal pads 105are distributed between bonding edge 111 and read edge 112. Wire bondpads 108 are located proximal to bonding edge 111. In some embodiments,relay pads 106 are adjacent to wire bond pads 108 and positioned betweenwire bond pads 108 and power terminal pads 105. The broken lines in FIG.1B indicate connecting traces (109 in FIG. 1A) connecting relay pads 106to wire bond pads 108. In some embodiments, the connecting traces areembedded under top surfaced 107. Die 101 a is below die 101 b in diestack 100. Die 101 a and die 101 b are separated by an intervening layerof DPDAF (102 in FIG. 1A), which not shown in FIG. 1B. In someembodiments, die stack 100 is disposed on package substrate 113, uponwhich bond finger 114 is disposed near bonding edge 111 of dies 101 aand 101 b. In some embodiments, package substrate 113 comprisesBakelite, epoxy, or build-up film. In some embodiments, power terminalpads 105 and relay pad 106 are identically configured on die 101 a.

Power terminal pads 105 and relay pads 106, as well as wire bond pads108 may comprise materials such as, but not limited to, copper, copperalloys, aluminum and alloys of aluminum, nickel, and polysilicon. Insome embodiments, power terminal pads 105 may be a single pad disposedon top surface 107. In some embodiments, power terminal pads 105 may bea plurality of pads disposed on top surface 107, as shown in FIG. 1B.One or more relay pads 106 may be present, as indicated in FIG. 1B. Insome embodiments, power terminal pads 105 are part of one or moreintegrated circuits incorporated on the dies (100 a and 100 b). As anexample, power terminal pads 105 are coupled to a V_(DD) power rail. Insome embodiments, relay pads 106 are disposed near bonding edge 111. Insome embodiments, relay pads 106 are electrically coupled to one or morewire bond pads 108.

Advantageously, conductive adhesive layer 104 of DPDAF 102 provides anexternal low resistance path coupling power terminal pads 105 to relaypads 106, eliminating the need for power traces coupling wire bond pads108 and power terminal pads 105. The reduction or elimination of powertraces may allow more choices for signal routing and increase signaltrace routing density. In some embodiments, conductive adhesive layer104 has a thickness ranging from 1 to 50 microns and a width extendingup to the width of the die. Due to the relatively large cross-sectionaldimensions of conductive adhesive layer 104, the sheet resistance may besignificantly lower than that of traditional metal traces, allowingsignificantly larger currents to be distributed to power terminal pads105. DLDAF 102 enables design of integrated circuits having one or moredistributed power terminals. As a consequence, the requirement for longand potentially higher resistance power traces is reduced, allowing ahigher density of power consuming devices, such as transistors andresistors, to be included in the integrated circuitry.

FIG. 2A illustrates a cross-sectional view of an exemplary shingle diestack assembly 200 a having a spacer die on top, with double layer dieattach film (DLDAF) layers between adjacent dies, according to someembodiments of the disclosure.

FIG. 2A illustrates one example of a complete die stack assembly 200 inshingle stacking configuration. In shingle stacking, edges 112 of dies101 a, 101 b and 101 c, including spacer die 201, are offset. Spacer die201 caps die stack 200 comprising dies 101 a, 101 b and 101 c, which areactive dies according to some embodiments. In some embodiments, spacerdie 201 is disposed above top active die 101 c, and provides a cap fornon-conductive adhesive layer 103 of the topmost DLDAF layer 102 c.Wires 202 are bonded at a first end to wire bond pads 108 on dies 101 a,101 b and 101 c. Wires 202 are bonded at a second end to bond finger 114disposed on package substrate 113. In some embodiments, wires 202provide power connections from power distribution metallization coupledto bond finger 114 on package substrate 113.

In some embodiments, bond pads 108 are coupled to relay pad 106 throughtrace 109 as described above. In the illustrated embodiment of FIG. 2A,power is delivered from a power pin on package substrate 113 to relaypad 106 by wires 202. The shingle stack configuration of die stack 200 aexposes bond pads 108 for access to wire bonds. In the illustratedembodiment shown in FIG. 2A, die stack 200 a comprises three dies 101 a,101 b, and 101 c, however, the number of dies in die stack 200 a is notlimited, and any number of dies may be included in die stack 200 a.

FIG. 2B illustrate a cross-sectional view of an exemplary straight-updie stack 200 b assembly with dual-sided die attach film layers betweenadjacent dies, according to some embodiments of the disclosure.

In FIG. 2B, an example of a straight-up stack 200 b having dies 101 a,101 b, 101 c and spacer die 201 are arranged with edges 112 aligned. Thestraight-up die stack architecture decreases x-y package footprint,facilitating further miniaturization of computing and analog devices.Wires 202 are bonded to wire bond pads 108, which are embedded withinconductive adhesive layer 104 of DLDAF 102. As with FIG. 2A, spacer die201 is present in some embodiments to cap die stack 200 b and covernon-conductive adhesive layer 103 of topmost DLDAF 102 c.

In some embodiments, wires 202 are each bonded at a first send to bondpads 108, and at a second end, to bond finger 114 on package substrate113. In other embodiments, wires 202 are bonded to wire bond pads 108 onadjacent or non-adjacent dies 101 a-101 c within die stack 200 b.

FIG. 3A illustrates a cross-sectional view of a portion of double-layerdie attach film 102, according to some embodiments of the disclosure.

In FIG. 3A, a portion of DLDAF 102 is shown. According to someembodiments, conductive adhesive layer 104 and non-conductive adhesivelayer 103 are adjacent layers, and comprise a polymer matrix impregnatedwith adhesive compounds. In some embodiments, conductive adhesive layer104 comprises conductive particulates of graphite, gold and silver. Insome embodiments, DLDAF 102 comprises a partially cured thermosetpolymer resin that is cured to a solid die attach layer after the diestack is assembled to permanently hold the die stack in a rigidconfiguration.

FIG. 3B illustrates a cross-sectional view of a portion of triple layerdie attach film 300, according to some embodiments of the disclosure.

In FIG. 3B, triple layer die attach film 300 (TLDAF) 300 comprises anon-conductive layer 103 is sandwiched between two conductive adhesivelayers 104. In some embodiments, conductive adhesive layers 104 aresubstantially identical, comprising conductive particulates, such as,but not limited to, graphite, gold and silver. Similar to DLDAF 102 inFIG. 3A, TLDAF 300 comprises a polymer matrix. In some embodiments,TLDAF 300 comprises a thermoplastic polymer resin that hardens uponheating. As will be shown below, TLDAF 300 may be employed for dieshaving power terminal pads on both top and bottom surfaces, whereconductive adhesive layers may contact the active surfaces of upper andlower adjacent dies in the stack.

FIG. 3C illustrates a plan view of die 310 covered by a section ofdouble layer die attach film (DLDAF) showing an exemplary currentdistribution through conductive adhesive layer 104, according to someembodiments of the disclosure.

In FIG. 3C, coverage of metallization comprising power pad terminals(e.g., 105 in FIG. 1B) and relay pads (e.g., 106 in FIG. 1B) byconductive adhesive layer 104 (of DLDAF 102 or TLDAF 300) is shown. InFIG. 3C, conductive adhesive layer 104 is partially transparent to showunderlying power terminal pads 105 and relay pads 106 in a configurationsimilar to that shown in FIG. 1B. An example of current distributionfrom relay pads to power terminals as current is conducted throughconductive adhesive layer 104. Dashed curves along top surface 107 ofdie 101 demonstrate an exemplary current distribution from relay pads106 to power terminal pads 105. The current distribution shows thatcurrent may spread from a single relay pad 106 to multiple powerterminal pads 105. In some embodiments, multiple relay pads 106simultaneously deliver power to power terminal pads 105, allowingsymmetric current distribution patterns to emerge through conductiveadhesive layer 104, as shown in FIG. 3C. In this way, heat distributionmay also be balanced over the die top surface 107, preventing hot spotson the die.

FIG. 4 illustrates a cross-sectional view of an exemplary shingle diestack 400 with triple layer die attach film between adjacent dual-sideddies, according to some embodiments of the disclosure.

In FIG. 4, die stack 400 comprises double-sided dies 401, having powerterminal pads 105 and rely pads 106 disposed on both sides. In thisimplementation, triple layer die attach film (TLDAF) 300 is disposedbetween dies 401 a, 401 b and 401 c, contacting power terminal pads 105and relay pads 106 on both sides of dies 401. Die stack 400 is cappedwith spacer die 201. Beneath spacer die 201 is double layer die attachfilm (DLDAF) 102 between spacer die 201 to die 401 a. Similarly, DLDAF102 is inserted between die stack 400 and package substrate 113, wherenon-conductive layer 103 cements die stack 400 to package substrate 113,while coupling power terminal pads 105 and relay pads 106 on the bottomside of die 401 c.

In some embodiments, all power terminal pads 105 disposed on a side ofdies 401 a-401 c are coupled to each other through conductive adhesivelayer 104, and therefore at the substantially the same potential. Insome embodiments, portions of power terminal pads 105 are coupledthrough separate portions of double layer die attach film. As anexample, in some embodiments, one portion of power terminal pads 105 arecoupled to a positive voltage rail on substrate 113. Another portion ofpower terminal pads 105 are coupled to a ground rail on substrate 113.In some embodiments, power terminal pads 105 on top surface 107 arecoupled to a positive or negative voltage rail on substrate 113, andpower terminals 105 on bottom surface 110 of dies 401 a, 401 b, and 401c are coupled to a ground rail on substrate 113.

FIG. 5 illustrates a flow chart 500 describing a process flow forassembling a die stack with DLDAF, according to some embodiments of thedisclosure.

In FIG. 5, several steps are shown for assembly of a die stackcomprising DLDAF (102) or TLDAF (300). At operation 501, singulated diesare received and transferred to a front of line (FOL) package assembly.In some embodiments, the dies have power terminal pads and relay pads onone side. In other embodiments, the dies have power terminal pads andrelay pads on both sides.

At operation 502, The die stack formation begins with substratepreparation. A substrate upon which the die stack is to be assembledundergoes a prebake step. In some embodiments, a buildup film isemployed as the substrate. In other embodiments, an epoxy material isemployed as a substrate. In some embodiments, the prebake step is tocure the substrate material.

At operation 503, the die stack is assembled. In some embodiments, thestack assembled in a shingle configuration. In some embodiments, thestack is assembled in a straight up configuration. Die attach isaccomplished with DLDAF for single-sided dies, or TLDAF for double-sideddies. In some embodiments, the DLDAF or TLDAF is partially cured toremain malleable in order to maintain a degree of tackiness for adhesionto the surface of the dies. Die attachment may be facilitated by pickand place techniques. However, other die stack assembly methods may beemployed to build the die stack. In some embodiments, the bottom-mostdie of the stack is a single sided die, and is attached to the substrateis using standard (non-conducting single layer) DAF. The bottom side ofthe single sided die is inactive, having no metallization. Aconventional die attach film may be employed to anchor the first die tothe substrate.

In some embodiments, the bottom-most die of the stack is a double-sideddie. In some embodiments, the bottom die has metallization. In someembodiments, power terminal pads as well as relay pads are distributedon the bottom surface of the die. In some embodiments, a DLDAF attachesthe die to the substrate, where the conductive adhesive layer of theDLDAF is attached to the bottom side of the die. The non-conductiveadhesive layer of the DLDAF is attached to the substrate.

Returning to operation 503, dies are added to the stack in alternatingsuccession of die attach film as DLDAF or TLDAF to the topmost die, thenplacement of a die onto the die attach film. In some embodiments, aDLDAF or TLDAF layer is attached to the top surface of the bottom-mostdie of the stack. The choice of DLDAF or TLDAF depends on the stackarchitecture. In some embodiments, the die stack is comprised entirelyof single-sided dies. In some embodiments, the die stack is comprisedentirely of double-sided dies. In some embodiments, the die stack iscomprised of some single sided dies and some double-sided dies.

Placement of a single sided die on the growing die stack presents itsbottom side, which is an inactive surface with no metallization, abovethe metallized surface of a single-sided or double-sided lower adjacentdie. In some embodiments, the bottom side of the single-sided diecomprises semiconductor material and is conductive. In some embodiments,the die stack is assembled by first placing a layer of DLDAF with theconductive adhesive layer face down over the top-most die of the diestack, followed by placement of a single-sided die on the non-conductiveadhesive layer of the DLDAF layer.

Placement of a double-sided die on the growing die stack presents itsbottom side, which is a metallized die surface, over the metallized diesurface from the lower adjacent die in a vertical stack. In someembodiments, the die stack is assembled by first placing a layer ofTLDAF layer on the top-most die, followed by placement of a double-sideddie on the growing stack.

At the termination of the assembly process, a spacer die is placed overthe top-most active die in the die stack, according to some embodiments.In some embodiments, a layer of DLDAF with the conductive adhesive layerbottom-side is placed over the top surface of the top-most die in thedie stack. The conductive adhesive layer covers and adheres to the topsurface metallization (e.g., power terminal pads and relay pads). Thenon-conductive adhesive layer adheres to the spacer die above. The diestack is assembled at this point.

Referring now to operation 504 of FIG. 5, the die attachment film (e.g.,DLDAF and/or TLDAF) is cured at high temperature for a final cure. Insome embodiments, the cure step is carried out at 60° C.-70° C. In otherembodiments, the cure step is carried out at 75° C.-80° C. (time).During curing, the die attachment film hardens to form a rigid layer,cementing dies in the die stack into the particular configuration(shingle or straight up).

At operation 505, wire bonding is performed, where wires are bonded towire bond pads (e.g., 108 in FIG. 1A) on the bonding edges of dies inthe die stack and the bond finger disposed on the package substrate. Insome embodiments, the die stack configuration is a shingleconfiguration, and wire bonding is performed after operation 504, curingthe die attachment film. In some embodiments, the die stackconfiguration is a straight up configuration. In some embodiments, wirebonding is performed after attachment of each die on a growing straightup die stack. Wire bonding may be performed by standard wire bondingmethods.

FIGS. 6A-6F illustrate cross-sectional views of an exemplary method forassembling a shingle die stack 200 a, according to some embodiments.

In FIG. 6A, the assembly of die stack 200 a begins with die 101 aattached to substrate 113. In some embodiments, die 101 a is a singlesided die, as illustrated. In some embodiments, substrate 113 isprepared in operation 502 of process flow 500 (FIG. 5). Die 101 a isattached to substrate 113 by any number of suitable methods. In someembodiments, die 101 is attached with die attach film. In someembodiments, the die attach film is standard single layer insulatingadhesive film. In some embodiments, die 101 a is a double-sided die,attached to substrate 113 by a layer of DLDAF.

In FIG. 6B, a first layer of DLDAF 102 a is attached to die 101 a withnon-conductive layer 103 facing upward. As the stack configuration isshingle, DLDAF 102 a is offset in the x-dimension relative to die 101 a.Conductive adhesive layer 104 covers power terminal pads 105 and relaypad 106. In FIG. 6C, second die 101 b is attached to DLDAF 102 a.Attachment may be accomplished by pick and place techniques. Die 101 bis attached to non-conductive adhesive layer 103 with edges aligned,according to some embodiments. In some embodiments, die stack 200 a isassembled as a straight-up die stack, such as shown in FIG. 2B, whereedges 112 are aligned.

In FIG. 6D, the operations illustrated in FIG. 6B and FIG. 6C have beenrepeated two more times each to arrive at the structure shown. In someembodiments, dies 101 b and 101 c have been added in alternatingsuccession with DPDAF layers 102 b and 102 c, with an offset in thex-dimension. Non-conductive adhesive layer 103 of DPDAF layer 102 c isexposed. In FIG. 6E, spacer die 201 is attached over DPDAF 102 c to capdie stack 200 a, according to some embodiments. Spacer die 201 isattached to non-conductive adhesive layer 103 of DPDAF layer 102 c. Insome embodiments, spacer die 201 is omitted. In some embodiments, acuring operation (not shown) may be performed after die stack assemblyto solidify the DLDAF, resulting in a rigid die stack.

In FIG. 6F, wires 202 are bonded to bond pads 108 after die stack 200 ais assembled. Wire bonding may be performed after a curing step by anynumber of techniques. In some embodiments, wires are ball bonded to thedie bond pads (108) and stitch-bonded to the bond finger (114) onsubstrate 113. In some embodiments, wires are bonded to each die duringbuilding of die stack 200 a.

FIG. 7 illustrates a package with a SCSP package comprising a DLDAF or aTLDAF in a vertical die stack, connecting multiple dies as part of asystem-on-chip (SoC) package in an implementation of computing device700, according to some embodiments of the disclosure.

FIG. 7 illustrates a block diagram of an embodiment of a mobile devicein which flat surface interface connectors could be used. In someembodiments, computing device 700 represents a mobile computing device,such as a computing tablet, a mobile phone or smart-phone, awireless-enabled e-reader, or other wireless mobile device. It will beunderstood that certain components are shown generally, and not allcomponents of such a device are shown in computing device 700.

In some embodiments, computing device 700 includes a first processor710. The various embodiments of the present disclosure may also comprisea network interface within 770 such as a wireless interface so that asystem embodiment may be incorporated into a wireless device, forexample, cell phone or personal digital assistant.

In one embodiment, processor 710 can include one or more physicaldevices, such as microprocessors, application processors,microcontrollers, programmable logic devices, or other processing means.The processing operations performed by processor 710 include theexecution of an operating platform or operating system on whichapplications and/or device functions are executed. The processingoperations include operations related to I/O (input/output) with a humanuser or with other devices, operations related to power management,and/or operations related to connecting the computing device 700 toanother device. The processing operations may also include operationsrelated to audio I/O and/or display I/O.

In one embodiment, computing device 700 includes audio subsystem 720,which represents hardware (e.g., audio hardware and audio circuits) andsoftware (e.g., drivers, codecs) components associated with providingaudio functions to the computing device. Audio functions can includespeaker and/or headphone output, as well as microphone input. Devicesfor such functions can be integrated into computing device 700, orconnected to the computing device 700. In one embodiment, a userinteracts with the computing device 700 by providing audio commands thatare received and processed by processor 710.

Display subsystem 730 represents hardware (e.g., display devices) andsoftware (e.g., drivers) components that provide a visual and/or tactiledisplay for a user to interact with the computing device 700. Displaysubsystem 730 includes display interface 732 which includes theparticular screen or hardware device used to provide a display to auser. In one embodiment, display interface 732 includes logic separatefrom processor 710 to perform at least some processing related to thedisplay. In one embodiment, display subsystem 730 includes a touchscreen (or touch pad) device that provides both output and input to auser.

I/O controller 740 represents hardware devices and software componentsrelated to interaction with a user. I/O controller 740 is operable tomanage hardware that is part of audio subsystem 720 and/or displaysubsystem 730. Additionally, I/O controller 740 illustrates a connectionpoint for additional devices that connect to computing device 700through which a user might interact with the system. For example,devices that can be attached to the computing device 700 might includemicrophone devices, speaker or stereo systems, video systems or otherdisplay devices, keyboard or keypad devices, or other I/O devices foruse with specific applications such as card readers or other devices.

As mentioned above, I/O controller 740 can interact with audio subsystem720 and/or display subsystem 730. For example, input through amicrophone or other audio device can provide input or commands for oneor more applications or functions of the computing device 700.Additionally, audio output can be provided instead of, or in addition todisplay output. In another example, if display subsystem 730 includes atouch screen, the display device also acts as an input device, which canbe at least partially managed by I/O controller 740. There can also beadditional buttons or switches on the computing device 700 to provideI/O functions managed by I/O controller 740.

In one embodiment, I/O controller 740 manages devices such asaccelerometers, cameras, light sensors or other environmental sensors,or other hardware that can be included in the computing device 700. Theinput can be part of direct user interaction, as well as providingenvironmental input to the system to influence its operations (such asfiltering for noise, adjusting displays for brightness detection,applying a flash for a camera, or other features).

In one embodiment, computing device 700 includes power management 750that manages battery power usage, charging of the battery, and featuresrelated to power saving operation. Memory subsystem 760 includes memorydevices for storing information in computing device 700. Memory caninclude nonvolatile (state does not change if power to the memory deviceis interrupted) and/or volatile (state is indeterminate if power to thememory device is interrupted) memory devices. Memory subsystem 760 canstore application data, user data, music, photos, documents, or otherdata, as well as system data (whether long-term or temporary) related tothe execution of the applications and functions of the computing device700.

Elements of embodiments are also provided as a machine-readable medium(e.g., memory 760) for storing the computer-executable instructions. Themachine-readable medium (e.g., memory 760) may include, but is notlimited to, flash memory, optical disks. CD-ROMs, DVD ROMs, RAMs,EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM),or other types of machine-readable media suitable for storing electronicor computer-executable instructions. For example, embodiments of thedisclosure may be downloaded as a computer program (e.g., BIOS) whichmay be transferred from a remote computer (e.g., a server) to arequesting computer (e.g., a client) by way of data signals via acommunication link (e.g., a modem or network connection).

Connectivity via network interface 770 includes hardware devices (e.g.,wireless and/or wired connectors and communication hardware) andsoftware components (e.g., drivers, protocol stacks) to enable thecomputing device 700 to communicate with external devices. The computingdevice 700 could be separate devices, such as other computing devices,wireless access points or base stations, as well as peripherals such asheadsets, printers, or other devices.

Network interface 770 can include multiple different types ofconnectivity. To generalize, the computing device 700 is illustratedwith cellular connectivity 772 and wireless connectivity 774. Cellularconnectivity 772 refers generally to cellular network connectivityprovided by wireless carriers, such as provided via GSM (global systemfor mobile communications) or variations or derivatives, CDMA (codedivision multiple access) or variations or derivatives, TDM (timedivision multiplexing) or variations or derivatives, or other cellularservice standards. Wireless connectivity (or wireless interface) 774refers to wireless connectivity that is not cellular, and can includepersonal area networks (such as Bluetooth, Near Field, etc.), local areanetworks (such as Wi-Fi), and/or wide area networks (such as WiMax), orother wireless communication.

Peripheral connections 780 include hardware interfaces and connectors,as well as software components (e.g., drivers, protocol stacks) to makeperipheral connections. It will be understood that the computing device700 could both be a peripheral device (“to” 782) to other computingdevices, as well as have peripheral devices (“from” 784) connected toit. The computing device 700 commonly has a “docking” connector toconnect to other computing devices for purposes such as managing (e.g.,downloading and/or uploading, changing, synchronizing) content oncomputing device 700. Additionally, a docking connector can allowcomputing device 700 to connect to certain peripherals that allow thecomputing device 700 to control content output, for example, toaudiovisual or other systems.

In addition to a proprietary docking connector or other proprietaryconnection hardware, the computing device 700 can make peripheralconnections 780 via common or standards-based connectors. Common typescan include a Universal Serial Bus (USB) connector (which can includeany of a number of different hardware interfaces), DisplayPort includingMiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI),Firewire, or other types.

Reference in the specification to “an embodiment,” “one embodiment,”“some embodiments,” or “other embodiments” means that a particularfeature, structure, or characteristic described in connection with theembodiments is included in at least some embodiments, but notnecessarily all embodiments. The various appearances of “an embodiment,”“one embodiment,” or “some embodiments” are not necessarily allreferring to the same embodiments. If the specification states acomponent, feature, structure, or characteristic “may,” “might,” or“could” be included, that particular component, feature, structure, orcharacteristic is not required to be included. If the specification orclaim refers to “a” or “an” element, that does not mean there is onlyone of the elements. If the specification or claims refer to “anadditional” element, that does not preclude there being more than one ofthe additional element.

Furthermore, the particular features, structures, functions, orcharacteristics may be combined in any suitable manner in one or moreembodiments. For example, a first embodiment may be combined with asecond embodiment anywhere the particular features, structures,functions, or characteristics associated with the two embodiments arenot mutually exclusive.

While the disclosure has been described in conjunction with specificembodiments thereof, many alternatives, modifications and variations ofsuch embodiments will be apparent to those of ordinary skill in the artin light of the foregoing description. The embodiments of the disclosureare intended to embrace all such alternatives, modifications, andvariations as to fall within the broad scope of the appended claims.

In addition, well known power/ground connections to integrated circuit(IC) chips and other components may or may not be shown within thepresented figures, for simplicity of illustration and discussion, and soas not to obscure the disclosure. Further, arrangements may be shown inblock diagram form in order to avoid obscuring the disclosure, and alsoin view of the fact that specifics with respect to implementation ofsuch block diagram arrangements are highly dependent upon the platformwithin which the present disclosure is to be implemented (i.e., suchspecifics should be well within purview of one skilled in the art).Where specific details (e.g., circuits) are set forth in order todescribe example embodiments of the disclosure, it should be apparent toone skilled in the art that the disclosure can be practiced without, orwith variation of, these specific details. The description is thus to beregarded as illustrative instead of limiting.

The following examples pertain to further embodiments. Specifics in theexamples may be used anywhere in one or more embodiments. All optionalfeatures of the apparatus described herein may also be implemented withrespect to a method or process.

Example 1 is an apparatus, comprising a die stack comprising at leastone die pair, the at least one die pair having a first die over a seconddie, the first die and the second die both having a first surface and asecond surface, the second surface of the first die over the firstsurface of the second die, and an adhesive film between the first dieand the second die of the at least one die pair; wherein the adhesivefilm comprises an insulating layer and a conductive layer, theinsulating layer adhering to the second surface of the first die and theconductive layer adhering to the first surface of the second die.

Example 2 includes all of the features of example 1, wherein one or moreelectrical contact pads are on the first surface of the first die andthe first surface of the second die, and wherein at least a portion ofthe one or more electrical contact pads are electrically coupled by theconductive layer of the adhesive film.

Example 3 includes all of the features of example 2, wherein the one ormore contact pads on the first surface of the first die and the firstsurface of the second die comprise at least one power terminal and atleast one edge bond pad.

Example 4 includes all of the features of example 3, wherein thedistance between the at least one power terminal and the at least oneedge bond pad of the first die ranges between one third of the length ofthe first die and the length of the first die.

Example 5 includes all of the features of example 3, wherein thedistance between the at least one power terminal and the at least oneedge bond pad of the second die ranges between one third of the lengthof the second die and the length of the second die.

Example 6 includes all of the features of example 3, wherein the one ormore contact pads on the first surface of the first die and the firstsurface of the second die comprise at least one relay contact coupled tothe at least one edge bond pad on the by a metal interconnect, and theat least one power terminal is coupled to the at least one relay contactby the conductive adhesive layer.

Example 7 includes all of the features of example 1, wherein theadhesive film comprises an insulating layer between a first conductiveadhesive layer and a second conductive adhesive layer.

Example 8 includes all of the features of example 7, wherein the firstconductive adhesive layer adheres to the second surface of the firstdie, and the second conductive adhesive layer adheres to the firstsurface of the second die.

Example 9 includes all of the features of example 8, wherein one or morecontact pads are on the second surface of the first die and on the firstsurface of the second die, and wherein at least a portion of the one ormore contact pads on the second surface of the first die areelectrically coupled by the first conductive adhesive layer, and atleast a portion of the one or more contact pads on the first surface ofthe second die are electrically coupled by the second conductiveadhesive layer.

Example 10 includes all of the features of example 9, wherein the one ormore contact pads on the second surface of the first die comprise atleast one power terminal.

Example 11 includes all of the features of example 9, wherein the one ormore contact pads on the first surface of the second die comprise atleast one power terminal.

Example 12 includes all of the features examples 10 or 11, wherein theone or more contact pads comprise at least one relay contact coupled toan edge bond pad on the by a metal interconnect, and the at least onepower terminal is coupled to the at least one relay contact by theconductive adhesive layer.

Example 13 includes all of the features of examples 10 or 11, whereinthe distance between the at least one power terminal and the bond edgeof the first die ranges between one third of the length of the first dieand the length of the first die.

Example 14 includes all of the features of examples 10 or 11, whereinthe distance between the at least one power terminal and the bond edgeof the second die ranges between one third of the length of the seconddie and the length of the second die.

Example 15 includes all of the features of example 1 wherein theadhesive film is a laminate comprising an insulating layer and at leastone conductive layer.

Example 16 includes all of the features of any of examples 1 through 15,wherein one or more edges of the first die and the second die arelaterally offset.

Example 17 includes all of the features of any of examples 1 through 15,wherein the edges of the first die and the second die are aligned.

Example 18 includes all of the features of any of examples 1 through 15,wherein the die stack comprises a spacer die over the first die of theat least one die pair.

Example 19 is a system, comprising a memory, a processor coupled to thememory, and an apparatus comprising at least one die pair having a firstdie over a second die, the first die and the second die both having afirst surface and a second surface, the second surface of the first dieover the first surface of the second die, and an adhesive film betweenthe first die and the second die of the at least one die pair, whereinthe adhesive film comprises an insulating layer adhering to the secondsurface of the first die and the conductive layer adhering to the firstsurface of the second die.

Example 20 includes all of the features of example 19, wherein one ormore electrical contact pads are on the first surface of the first dieand the first surface of the second die, and wherein at least a portionof the one or more electrical contact pads are electrically coupled bythe conductive layer of the adhesive film.

Example 21 includes all of the features of example 20, wherein the oneor more contact pads on the first surface of the first die and the firstsurface of the second die comprise at least one power terminal and atleast one edge bond pad.

Example 22 includes all of the features of example 21, wherein thedistance between the at least one power terminal and the bond pad edgeof the first die ranges between one third of the length of the first dieand the length of the first die.

Example 23 includes all of the features of example 21, wherein thedistance between the at least one power terminal and the bond pad edgeof the second di range between one third of the length of the second dieand the length of the second die.

Example 24 includes all of the features of examples of any one of 20through 23, wherein the one or more contact pads on the first surface ofthe first die and the first surface of the second die comprise at leastone relay contact coupled to the at least one edge bond pad by aninterconnect, and the at least one power terminal is coupled to the atleast one relay contact by the conductive adhesive layer.

Example 25 is a method comprising receiving a first die having a firstsurface and a second surface, attaching a first adhesive film having aninsulating layer and a conductive layer to the first die, wherein theconductive layer is attached to the first surface of the first die,receiving a second die having a first surface and a second surface,attaching a second adhesive film having an insulating layer and aconductive layer to the second die, wherein the conductive layer isattached to the first surface of the second die, and attaching thesecond surface of the second die to the insulating layer of the firstadhesive film attached to the first die.

Example 26 includes all of the features of example 25, furthercomprising receiving a spacer die having a first surface and a secondsurface, attaching the spacer die to the insulating layer of the secondadhesive film, and curing the first adhesive film and the secondadhesive film.

Example 27 includes all of the features of examples 25 or 26, whereinreceiving a first die comprises receiving a first die attached to asubstrate.

Example 28 includes all of the features of example 25, wherein receivinga first die having a first surface and a second surface comprisesreceiving a first die having one or more power terminals disposed on thefirst surface.

Example 29 includes all of the features of example 28, wherein attachinga first film having an insulating layer and a conductive layer to thefirst die comprises adhering the conductive layer of the first adhesivefilm to the one or more power terminals disposed on the first surface ofthe first die.

Example 30 includes all the features of example 25, wherein receiving asecond die having a first surface and a second surface comprisesreceiving a second die having one or more power terminals disposed onthe first surface.

Example 31 includes all of the features of example 30, wherein attachinga second adhesive film having an insulting layer of the second adhesivefilm to the one or more power terminals disposed on the first surface ofthe second die.

An abstract is provided that will allow the reader to ascertain thenature and gist of the technical disclosure. The abstract is submittedwith the understanding that it will not be used to limit the scope ormeaning of the claims. The following claims are hereby incorporated intothe detailed description, with each claim standing on its own as aseparate embodiment.

We claim:
 1. An apparatus, comprising: an integrated circuit (IC) diestack comprising at least a first die under a second die; and amulti-layered film between the first die and the second die, wherein thefilm comprises an electrically conductive adhesive layer in contact witha first surface of the first die and an electrically insulative layeradhered to a second surface of the second die.
 2. The apparatus of claim1, wherein one or more first electrical contact pads on the firstsurface of the first die are in contact with the electrically conductiveadhesive layer.
 3. The apparatus of claim 2, wherein the firstelectrical contact pads comprise at least one power terminalelectrically coupled to at least one edge bond pad through theelectrically conductive adhesive layer.
 4. The apparatus of claim 3,wherein the power terminal and the edge bond pad are separated by afirst distance of at least one third of a length of the first die. 5.The apparatus of claim 3, wherein the first electrical contact padscomprise at least one relay contact coupled to the at least one edgebond pad through a metal interconnect trace within the first die, andwherein the relay contact is in direct contact with the electricallyconductive adhesive layer.
 6. The apparatus of claim 3, wherein theelectrically conductive adhesive layer is a first electricallyconductive adhesive layer, and the electrically insulative layer isbetween the first conductive adhesive layer and a second electricallyconductive adhesive layer.
 7. The apparatus of claim 6, wherein thefirst electrically conductive adhesive layer adheres to the firstsurface of the first die, and the second electrically conductiveadhesive layer adheres to the second surface of the second die.
 8. Theapparatus of claim 7, wherein one or more second electrical contact padson the second surface of the second die are electrically coupledtogether through the second electrically conductive adhesive layer. 9.The apparatus of claim 8, wherein: the second electrical contact padscomprise at least one second power terminal.
 10. The apparatus of claim9, wherein the second electrical contact pads comprise at least onesecond relay contact coupled to a second edge bond pad by a second metalinterconnect trace within the second die, and the wherein the secondrelay contact is in direct contact with the second electricallyconductive adhesive layer.
 11. The apparatus of claim 10, wherein: adistance between the power terminal and the edge bond pad is at leastone third of the length of the first die; and a distance between thesecond power terminal and the second edge bond pad is at least one thirdof the length of the second die.
 12. The apparatus of claim 10, whereinone or more edges of the first die and the second die are laterallyoffset, and wherein the apparatus further comprises a first wire bondedto the first edge bond pad, and a second wire bonded to the second edgebond pad.
 13. The apparatus of claim 10, wherein one or more edges ofthe first die and the second die are laterally aligned, and wherein theapparatus further comprises a first wire bonded to the first edge bondpad, and a second wire bonded to the second edge bond pad.
 14. Theapparatus of claim 1, wherein the die stack further comprises a spacerdie over the second die.
 15. A system comprising: a die stack comprisinga processor die over a memory die; a multi-layered film adhering theprocessor die to the memory die, wherein the film comprises two adhesivematerials, an electrically conductive one of the adhesive materials incontact with a first surface of the memory die and an electricallyinsulative one of the adhesive materials in contact with a secondsurface of the processor die; and a power supply coupled to theprocessor die.
 16. The system of claim 15, wherein one or moreelectrical contact pads are on the first surface of the memory die, andwherein at least a portion of the one or more electrical contact padsare electrically coupled together by the conductive adhesive layer. 17.A method, comprising: attaching an electrically conductive adhesivematerial layer of a multi-layered film to a first die; and attaching asecond die to an electrically insulative adhesive material layer of thefilm, wherein two or more contact pads on a first surface of the firstdie are electrically coupled together through the electricallyconductive adhesive material layer.
 18. The method of claim 17, whereinattaching the electrically conductive adhesive material layer comprisesadhering the electrically conductive adhesive layer to the two or morepower terminals, and wherein attaching the second die to theelectrically insulative adhesive material layer comprises adhering theelectrically insulative adhesive layer to a surface of the second die.19. The method of claim 18, further comprising attaching a secondelectrically conductive adhesive layer of a second film to second powerterminals of the second die, the second electrically conductive adhesivelayer of the second film electrically coupling together the second powerterminals.
 20. The method of claim 19, further comprising bonding a wireto an edge bond pad of the first die, the edge bond pad interconnectedto only one of the power terminals through an interconnect trace on thefirst die.